set company "Texas A&M university" set designer "654 Lab" set search_path "./" set hdlin_translate_off_skip_text TRUE #------ Library set link_library "* osu018_stdcells.db dw_foundation.sldb" set target_library "osu018_stdcells.db" set default_schematic_options "-size infinite" set synthetic_library "dw_foundation.sldb" set command_log_file "command.log" set view_command_log_file "view_command.log" set plot_command "lpr -Plw" set text_print_command "lpr -Plw" #define_design_lib WORK -path ./WORK set hdlin_source_to_gates_mode "high" set edifin_ground_name "VSS" set edifin_ground_net_name "VSS" set edifin_ground_net_property_name "global" set edifin_ground_net_property_value "VSS" set edifin_ground_pin_name "VSS" set edifin_ground_port_name "VSS" set edifin_netlist_only "true" set edifin_power_name "VDD" set edifin_power_net_name "VDD" set edifin_power_net_property_name "global" set edifin_power_net_property_value "VDD" set edifin_power_pin_name "VDD" set edifin_power_port_name "VDD" set edifin_power_and_ground_representation "net" set edifout_ground_name "VSS" set edifout_ground_net_name "VSS" set edifout_ground_net_property_name "global" set edifout_ground_net_property_value "VSS" set edifout_ground_pin_name "VSS" set edifout_ground_port_name "VSS" set edifout_netlist_only "true" set edifout_no_array "true" set edifout_power_name "VDD" set edifout_power_net_name "VDD" set edifout_power_net_property_name "global" set edifout_power_net_property_value "VDD" set edifout_power_pin_name "VDD" set edifout_power_port_name "VDD" set edifout_power_and_ground_representation "net" set write_name_nets_same_as_ports "true" set compile_fix_multiple_port_nets "true" set verilogout_no_tri "true" set sh_enable_line_editing true